This invention relates to a semiconductor memory cell suitable for memory cells of a dynamic RAM (random access memory).
A conventional memory cell used in the dynamic RAM as shown in FIG. 1 has been known. In the memory cell of FIG. 1, there are provided MOS transistor 1 for writing and reading out data and capacitor 2 for storing charges. One terminal of the source-drain path of the transistor is connected to a first electrode of capacitor 2. A second electrode of capacitor 2 is connected to bit line BL for data read and write. The gate of transistor 1 is connected to word line WL for data read and write. The second electrode of capacitor 2 is connected to a predetermined potential such as ground potential. To improve packing density of the memory device, further miniaturization is required for the cell. With this requirement, the capacitor must also be miniaturized. To increase the capacitance without increasing the capacitor area on the chip, a so-called trench capacitor is employed for capacitor 2.
The structure of the memory cell in FIG. 1 is illustrated in FIG. 2. Semiconductor regions 12 and 13 of N.sup.30 conductivity type are formed in the surface region of semiconductor substrate 11 of P conductivity type. Regions 12 and 13 form the source and drain regions of transistor 1, respectively. Trench 14 is formed at a predetermined location of substrate 11. Silicon oxide film 15, which serves as a dielectric and has a fixed thickness, is layered on the inner surface of trench 14. Polysilicon layer 16 is deposited on silicon oxide film 15. Polysilicon layer 16 forms the first electrode of capacitor 2. Reference numeral 17 designates the gate insulative film of transistor 1. Reference number 18 designates the gate electrode of transistor 1, and also serves as word line WL. Numeral 19 represents metal bit line BL made of aluminum, for example. Numeral 20 represents a field oxidation film for separating element regions. Capacitor 2 is formed in semiconductor substrate 11 in the form of the trench capacitor. With this structure of capacitor 2, the capacitor has a large capacitance although it occupies a small area on the chip.
The memory cell of a one transistor/one capacitor type as shown in FIGS. 1 and 2 has no problem in the data write operation, but is sensitive to noise in the data read out operation. The data read out operation is performed in a manner that the charges stored in capacitor 2 are read out onto bit line BL. The charges flow through two capacitors, capacitor 2 and parasitic capacitor 3 associated with bit line BL. Assuming that the capacitance of capacitor 2 is Cs and the capacitance of parasitic capacitor 3 is Cb, potential V.sub.BL on bit line BL is given as: EQU V.sub.VL =Cb/(Cs+Cb).
Usually in the semiconductor memory, a number of memory cells are connected to bit line BL. Therefore, capacitance Cb is larger than capacitance Cs, and Cb/Cs is about 20. For this reason, the potential of data, i.e. charges written into capacitor 2 by applying 5 V to bit line BL, decreases to 0.25 V or less when it is read out. This minute potential is sensed by a sense amplifier (not shown) connected to bit line BL.
As the number of memory cells connected to bit line BL increases, the capacitance of parasitic capacitor 3 increases. As the size of each element is further decreased, the capacitance of capacitor 2 is decreased, and hence the potential V.sub.BL detected is made smaller. This fact causes a serious problem in increasing the packing density.
To cope with this problem, there has been proposed a two-transistor dynamic memory cell of the current read out type, as shown in FIG. 3. When compared with the memory cell shown in FIGS. 1 and 2, in this type of memory cell, capacitor 2 is removed, while MOS transistor 4 for reading out data is added. One terminal of the source-drain path of transistor 4 is coupled with bit line BL, the other of them to word line RW. The gate of transistor 4 is coupled with one terminal of the source-drain path of transistor 1. The gate of transistor 1 is connected to word line WW for writing data.
In operation, when a write signal is applied to word line WW, transistor 1 is turned on, so that signal charges as data of logical "1" is held in the gate of transistor 4. For reading out data, a read signal is applied to word line RW. At this time, if signal charges have been stored in the gate of transistor 4, current is fed from word line RW to bit line BL through transistor 4. With this current, parasitic capacitor 3 is charged to increase the potential on bit line BL. The data is detected by sensing this potential by a sense amplifier. In the memory cell of prior art, two separate transistors 1 and 4 must be fabricated. As the result of the requirement of separate transistors fabrication, the area needed for these transistors is large, hindering packing density improvement.